The typical N.times.1 multiplexer chip consists of N analog, switched buffers 10 of which the output nodes are tied together as shown in FIG. 1.
During normal operations, one, at most, of the N channels is conductive and serves as the analog signal path passing either I1, I2 or I3 to the output terminal OUT.
End users of such circuits desiring to implement M.times.1 multiplexing on a PC board with a plurality of such N.times.1 multiplexer chips, with M&gt;N, generally connect the output terminal of the N.times.1 multiplexers with a 50 .OMEGA. or 75 .OMEGA. transmission line, which is capacitively loaded by the disabled non-operating multiplexers.
When the circuit of FIG. 1 is operating and a single channel selected, the analog signal at the output terminal sees the input impedance of the next stage. In addition, it also sees the impedance of the transmission lines leading to the disabled multiplexers. The output signal travels along each of the transmission lines until it reaches the disabled stages which can be regarded as capacitance, from which it bounces back along the transmission line to the output terminal. The capacitive termination of transmission lines degrades the frequency response of such circuits because the impedance changes with the capacitance. Thus the larger the capacitance, the worse the frequency response and the smaller the bandwidth.
The practice of designing complementary multiplexers by connecting a plurality of individual analog buffers together is an obstacle to higher integration and high system bandwidth.
The individual analog buffer of the circuit of FIG. 1 may be as shown in the circuit of FIG. 2. Referring to FIG. 2, the input signal is applied to the base of complementary transistors Q1 and Q2 each of which is connected between a current source IA and IB respectively and an appropriate voltage source Vee and Vcc. One of the two transistors conducts in response to the polarity of an input signal IN, and the output signal is taken from the emitter of the enabled transistor and applied to the base of one of the transistors Q3 or Q4, which, when conducting, provides the output signal OUT.
It is accordingly an object of the present invention to obviate many of the problems of known multiplexers and to provide a novel multiplexer and method with dramatically reduced disabled capacitance.
It is another object of the present invention to provide a novel multiplexer and method with dramatically increased bandwidth, i.e., the multiplexing of signals at a higher frequency.
It is still another object of the present invention to provide a novel multiplexer and method in which the number of output channels may be increased without an increase in output capacitance.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.